1. Field of the Invention
The present invention relates to a device having a gap. More particularly, the present invention pertains to a method of filling a gap and a method for forming a memory device using the same.
2. Description of the Related Art
Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices according to whether stored data is retained even when power is turned off. A phase change memory device is a type of a nonvolatile memory device under development as a next generation memory device which may replace a flash memory device. The phase change memory device may include a phase change material, e.g., a chalcogenide, that may be maintained at one of a crystalline state or an amorphous state by heating or cooling to change the state by a phase transition. The phase change material may have a low resistance in a crystalline state and a high resistance in an amorphous state. A logic value of the phase change memory device may be determined to a binary 0 or 1 depending on a resistance value of the phase change material. The crystalline state of the phase change material may correspond to a set or logic 0, and the amorphous state thereof may correspond to a reset or logic 1.
FIGS. 1A through 1C illustrate sectional views of a semiconductor substrate of stages of a method for forming a phase change memory device according to related art.
Referring to FIGS. 1A through 1C, a phase change material layer 30 and an upper electrode layer 40 may be formed on a semiconductor substrate 10 in which a lower electrode 25 is contained. The phase change material layer 30 and the upper electrode layer 40 may be patterned to form a phase change material layer pattern 35 and an upper electrode 45. An interlayer insulating layer 50 may be formed to cover an entire surface of the substrate 10. A contact plug 55 may be formed to penetrate the interlayer insulating layer 50 and contact the upper electrode 45. A line 60 may be formed on the interlayer insulating layer 50 to be electrically connected with the contact plug 55.
The photolithography and etching processes illustrated in FIGS. 1A through 1C may limit the phase change material layer pattern 35 to a width D1 of about 100 nm or less. Also, since the width D1 of the phase change material layer pattern 35 may be larger than a width D2 of the lower electrode 25, the phase change material layer pattern 35 may contact an entire upper surface of the lower electrode 25. That is, the width of the phase change material layer pattern 35 may be large, and a contact area between the phase change material layer pattern 35 and the lower electrode 25 may also be large. Therefore, when the phase change material layer pattern 35 is heated or cooled to change to the crystalline state or the amorphous state, a large amount of power may be consumed with an accompanying large heat loss. This phenomenon may lower the operation characteristics of the phase change memory device.